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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
May 2005
RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Features
Single positive-supply operation with low power and shutdown modes 40% CDMA/WCDMA efficiency at +28 dBm average output power Compact lead-free compliant low-profile package (3.0 x 3.0 x 1.0 mm nominal) Internally matched to 50 and DC blocked RF input/output Meets CDMA2000-1XRTT/WCDMA performance requirements Meets HSDPA performance requirement
General Description
The RMPA1965 power amplifier module (PAM) is designed for CDMA, CDMA2000-1X, WCDMA and HSDPA personal communications system (PCS) applications. The 2 stage PAM is internally matched to 50 to minimize the use of external components and features a low-power mode to reduce standby current and DC power consumption during peak phone usage. High power-added efficiency and excellent linearity are achieved using our InGaP Heterojunction Bipolar Transistor (HBT) process.
Device
Functional Block Diagram
(Top View)
MMIC Vcc1 1 RF IN 2 Vmode 3 DC BIAS CONTROL Vref 4 INPUT MATCH OUTPUT MATCH 8 Vcc2 7 RF OUT 6 GND 5 GND
(paddle ground on package bottom)
(c)2005 Fairchild Semiconductor Corporation
1
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RMPA1965 Rev. I
RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Absolute Ratings1
Symbol
Vcc1, Vcc2 Vref Vmode Pin TSTG Supply Voltages Reference Voltage Power Control Voltage RF Input Power Storage Temperature
Parameter
Value
5.0 2.6 to 3.5 3.5 +10 -55 to +150
Units
V V V dBm C
Note: 1: No permanent damage with only one parameter set at extreme limit. Other parameters set to typical values.
Electrical Characteristics1
Symbol
f CDMA Operation SSg Gp Po PAEd Small-Signal Gain Power Gain Linear Output Power PAEd (digital) @ +28dBm PAEd (digital) @ +16dBm PAEd (digital) @ +16dBm Itot High Power Total Current Low Power Total Current Adjacent Channel Power Ratio ACPR1 ACPR2 1.25MHz Offset 2.25MHz Offset -50 -52 -60 -68 dBc dBc dBc dBc 28 16 40 9 21 460 120 26 27 24 dB dB dB dBm dBm % % % mA mA Po = 0dBm Po = +28 dBm; Vmode = 0V Po = +16dBm; Vmode 2.0V Vmode = 0V Vmode 2.0V Vmode = 0V Vmode 2.0V Vmode 2.0V, Vcc = 1.4V Po = +28dBm, Vmode = 0V Po = +16dBm, Vmode 2.0V IS-95 Po = +28dBm; Vmode = 0V Po = +16dBm; Vmode 2.0V Po = +28dBm; Vmode = 0V Po = +16dBm; Vmode 2.0V
Parameter
Operating Frequency
Min
1850
Typ
Max
1910
Units
MHz
Comments
General Characteristics VSWR NF Rx No 2fo-5fo S Input Impedance Noise Figure Receive Band Noise Power Harmonic Suppression3 Spurious Outputs2, 3 Ruggedness w/ Load Mismatch3 Tc Case Operating Temperature -30 2.0:1 4 -139 -50 -60 10:1 85 C Vmode 2.0V Po +28dBm No applied RF signal. dB dBm/Hz dBc dBc Po +28dBm; 1930 to 1990MHz Po +28dBm Load VSWR 5.0:1 No permanent damage.
DC Characteristics Iccq Iref Icc(off) Quiescent Current Reference Current Shutdown Leakage Current 45 5 1 5 mA mA A
Notes: 1. All parameters met at Tc = +25C, Vcc = +3.4V, Vref = 2.85V, f = 1880MHz and load VSWR 1.2:1, unless otherwise noted. 2. All phase angles. 3. Guaranteed by design.
2 RMPA1965 Rev. I
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Performance Data
High Power Mode (Vcc = 3.4V, Vref = 2.85V, Vmode = 0V) Frequency dependency (Pout = 28dBm)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Pout = 28dBm
32 31 30 29 28 27 26 25 24 23 22 1850
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Pout = 28dBm
45 44 43 42 41 40 39 38 37 36 35 1850
Gain (dB)
1880 Frequency (MHz)
1910
PAE (%)
1880 Frequency (MHz)
1910
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Pout = 28dBm
-40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 1850
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Pout = 28dBm
-50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 1850
ACPR1 (dBc)
1880 Frequency (MHz)
1910
ACPR2 (dBc)
1880 Frequency (MHz)
1910
Pout dependency (Frequency = 1880MHz)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Freq = 1880MHz
32 31 30 29 28 27 26 25 24 23 22
0 4 8 12 16 20 24 28 Pout (dBm)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Freq = 1880MHz
50 45 40 35 30 25 20 15 10 5 0 0 4 8 12 16 20 24 28 Pout (dBm)
Gain (dB)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Freq = 1880MHz
-40 -45 -50 -55 -60 -65 -70 -75 -80
0 4 8 12 16 20 24 28 Pout (dBm)
PAE (%) ACPR2 (dBc)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 0V, Freq = 1880MHz
-50 -55 -60 -65 -70 -75 -80 -85 -90 0 4 8 12 16 20 24 28 Pout (dBm)
ACPR1 (dBc)
3 RMPA1965 Rev. I
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Performance Data
Low Power Mode (Vcc = 3.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
32 31 30 29 28 27 26 25 24 23 22 1850 1880 Frequency (MHz) 1910
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
15 14 13 12 11 10 9 8 7 6 5 1850 1880 Frequency (MHz) 1910
Gain (dB)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
-40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 1850
PAE (%)
RMPA1965 3x3 US-PCS PAM Vcc = 3.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
-60 -62 -64 -66 -68 -70 -72 -74 -76 -78 -80 1850
ACPR1 (dBc)
1880 Frequency (MHz)
1910
ACPR2 (dBc)
1880 Frequency (MHz)
1910
Low Power Mode (Vcc=1.4V, Vref=2.85V, Vmode=2V, Pout=16dBm)
RMPA1965 3x3 US-PCS PAM Vcc=1.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
28 27 26 25 24 23 22 21 20 19 18 1850
RMPA1965 3x3 US-PCS PAM Vcc = 1.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
25 24 23 22 21 20 19 18 17 16 15 1850
Gain (dB)
1880 Frequency (MHz)
1910
PAE (%)
1880 Frequency (MHz)
1910
RMPA1965 3x3 US-PCS PAM Vcc = 1.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
-50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 1850
RMPA1965 3x3 US-PCS PAM Vcc = 1.4V, Vref = 2.85V, Vmode = 2V, Pout = 16dBm
-60 -62 -64 -66 -68 -70 -72 -74 -76 -78 -80 1850
ACPR1 (dBc)
ACPR2 (dBc)
1880 Frequency (MHz)
1910
1880 Frequency (MHz)
1910
4 RMPA1965 Rev. I
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Efficiency Improvement Applications
In addition to high-power/low-power bias modes, the efficiency of the PA module can be significantly increased at backed-off RF power levels by dynamically varying the supply voltage (Vcc) applied to the amplifier. Since mobile handsets and power amplifiers frequently operate at 10-20 dB back-off, or more, from maximum rated linear power, battery life is highly dependent on the DC power consumed at antenna power levels in the range of 0 to +16dBm. The reduced demand on transmitted RF power allows the PA supply voltage to be reduced for improved efficiency, while still meeting linearity requirements for CDMA modulation with excellent margin. High-efficiency DC-DC converters are now available to implement switched-voltage operation. With the PA module in low-power mode (Vmode = +2.0V) at+16dBm output power and supply voltages reduced from 3.4V nominal down to 1.2V, power-added efficiency is more than doubled from 9.5 percent to nearly 25 percent (Vcc = 1.2V) while maintaining a typical ACPR1 of -52dBc and ACPR2 of less than -61dBc. Operation at even lower levels of Vcc supply voltage are possible with a further restriction on the maximum RF output power.
Recommended Operating Conditions
Symbol
f Vcc1, Vcc2 Vref Supply Voltage Reference Voltage (Operating) (Shutdown) Bias Control Voltage (Low-Power) (High-Power) Linear Output Power (High-Power) (Low-Power) Case Operating Temperature -30
Parameter
Operating Frequency
Min
1850 3.0 2.7 0 1.8 0
Typ
3.4 2.85
Max
1910 4.2 3.1 0.5 3.0 0.5 +28 +16 +85
Units
MHz V V V V V dBm dBm C
Vmode
2.0
Pout
Tc
DC Turn-On Sequence
1) Vcc1 = Vcc2 = 3.4V (typical) 2) Vref = 2.85V (typical) 3) High-Power: Vmode = 0V (Pout > 16 dBm) Low-Power: Vmode = 2V (Pout < 16 dBm)
5 RMPA1965 Rev. I
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Evaluation Board Layout
1965 XYTT Z
Materials List
Qty
1 2 7 Ref 3 3 2 1 1 A/R A/R
Item No.
1 2 3 4 5 5 (Alt) 6 7 7 (Alt) 8 9
Part Number
G657691-1 V1 #142-0701-841 #2340-5211TN GRM39X7R102K50V ECJ-1VB1H102K C3216X5R1A335M GRM39Y5V104Z16V ECJ-1VB1C104K SN63 SN96 PC Board
Description
SMA Connector Terminals Assembly, RMPA1965 1000pF Capacitor (0603) 1000pF Capacitor (0603) 3.3F Capacitor (1206) 0.1F Capacitor (0603) 0.1F Capacitor (0603) Solder Paste Solder Paste
Vendor
Fairchild Johnson 3M Fairchild Murata Panasonic TDK Murata Panasonic Indium Corp. Indium Corp.
Evaluation Board Schematic
3.3 F Vcc1 SMA1 RF IN 50 ohm TRL Vmode Vref 1000 pF 0.1 F 4 9 (package base) 1000 pF 1 2 3 1000 pF 8 50 ohm TRL 3.3 F Vcc2 SMA2 RF OUT
1965 XYTT Z
6
7
5,6
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RMPA1965 Rev. I
RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Package Outline
I/O 1 INDICATOR TOP VIEW 1 8
1965 XYTT Z
FRONT VIEW 9 1.00mm BOTTOM VIEW
2 3.00 +.100 mm SQ. -.050 3
7
6
4
5
1 XY 965 T ZT
1.10mm MAX.
4X R.25mm 4 BACK SIDE SOLDER MASK 3 6 2.60mm 2 7 8 0.20mm DETAIL A TYP. 0.40mm 0.10mm 1 0.40mm 0.10mm 5 2 0.40mm
SEE DETAIL A 1.00mm
1
Signal Descriptions
Pin No.
1 2 3 4 5 6 7 8
Symbol
Vcc1 RF In Vmode Vref GND GND RF Out Vcc2 Supply Voltage to Input Stage RF Input Signal
Description
High-Power/Low-Power Mode Control Reference Voltage Ground Ground RF Output Signal Supply Voltage to Output Stage
7 RMPA1965 Rev. I
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
Applications Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE. Precautions to Avoid Permanent Device Damage: * Cleanliness: Observe proper handling procedures to ensure clean devices and PCBs. Devices should remain in their original packaging until component placement to ensure no contamination or damage to RF, DC and ground contact areas. * Device Cleaning: Standard board cleaning techniques should not present device problems provided that the boards are properly dried to remove solvents or water residues. * Static Sensitivity: Follow ESD precautions to protect against ESD damage: - A properly grounded static-dissipative surface on which to place devices. - Static-dissipative floor or mat. - A properly grounded conductive wrist strap for each person to wear while handling devices. * General Handling: Handle the package on the top with a vacuum collet or along the edges with a sharp pair of bent tweezers. Avoiding damaging the RF, DC, and ground contacts on the package bottom. Do not apply excessive pressure to the top of the lid. * Device Storage: Devices are supplied in heat-sealed, moisture-barrier bags. In this condition, devices are protected and require no special storage conditions. Once the sealed bag has been opened, devices should be stored in a dry nitrogen environment. Device Usage: Fairchild recommends the following procedures prior to assembly. * Dry-bake devices at 125C for 24 hours minimum. Note: The shipping trays cannot withstand 125C baking temperature. * Assemble the dry-baked devices within 7 days of removal from the oven. * During the 7-day period, the devices must be stored in an environment of less than 60% relative humidity and a maximum temperature of 30C * If the 7-day period or the environmental conditions have been exceeded, then the dry-bake procedure must be repeated. Solder Materials & Temperature Profile: Reflow soldering is the preferred method of SMT attachment. Hand soldering is not recommended. Reflow Profile * Ramp-up: During this stage the solvents are evaporated from the solder paste. Care should be taken to prevent rapid oxidation (or paste slump) and solder bursts caused by violent solvent out-gassing. A typical heating rate is 1- 2C/sec. * Pre-heat/soak: The soak temperature stage serves two purposes; the flux is activated and the board and devices achieve a uniform temperature. The recommended soak condition is: 120-150 seconds at 150C. * Reflow Zone: If the temperature is too high, then devices may be damaged by mechanical stress due to thermal mismatch or there may be problems due to excessive solder oxidation. Excessive time at temperature can enhance the formation of inter-metallic compounds at the lead/board interface and may lead to early mechanical failure of the joint. Reflow must occur prior to the flux being completely driven off. The duration of peak reflow temperature should not exceed 10 seconds. Maximum soldering temperatures should be in the range 215- 220C, with a maximum limit of 225C. * Cooling Zone: Steep thermal gradients may give rise to excessive thermal shock. However, rapid cooling promotes a finer grain structure and a more crack-resistant solder joint. The illustration below indicates the recommended soldering profile. Solder Joint Characteristics: Proper operation of this device depends on a reliable void-free attachment of the heat sink to the PWB. The solder joint should be 95% void-free and be a consistent thickness. Rework Considerations: Rework of a device attached to a board is limited to reflow of the solder with a heat gun. The device should not be subjected to more than 225C and reflow solder in the molten state for more than 5 seconds. No more than 2 rework operations should be performed.
Recommended Solder Reflow Profile
240 220 200 183C 180 160 140 DEG (C) 120 100 80 60 40 20 0 0 60 120 TIME (SEC) 180 240 300 1C/SEC SOAK AT 150C FOR 60 SEC 45 SEC (MAX) ABOVE 183C 1C/SEC 10 SEC
8 RMPA1965 Rev. I
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RMPA1965 US-PCS CDMA, CDMA2000-1X and WCDMA PowerEdgeTM Power Amplifier Module
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM FAST ActiveArrayTM FASTrTM BottomlessTM FPSTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM EnSignaTM i-LoTM FACTTM ImpliedDisconnectTM FACT Quiet SeriesTM
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POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER SMART STARTTM
SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET UniFETTM VCXTM
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I15
9 RMPA1965 Rev. I
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